Programmable logic devices (PLD) such as field programmable gate arrays (FPGA) and complex programmable logic devices (CPLD) are digital logic circuits that can be programmed by certain “programming patterns” such as programmable object files (POFs) to perform logical functions. These devices have grown significantly in capability and complecity. Yet intellectual property (IP) protection embedded in such devices, such as the programming patterns, has not enjoyed similar development.
Currently, most IP protection schemes rely on encrypting/decrypting the programming patterns on chip. FIG. 1 shows a typical encryption/decryption IP protection scheme that includes a decrypter 120 that receives an encrypted POF 110 and a decryption key 160. The encrypted POF 110 is decrypted by the decrypter 120 using decryption key 160. The decrypted POF 130 is then used to program a programmable logic circuit 140. An output 170 of the programmable logic circuit 140 is coupled to a utility circuit 150. The drawback of this IP protection scheme is that it relies on a decryption key 160, which must be stored somewhere on the chip. As a result, this IP protection scheme is vulnerable to attack because it is not difficult for an attacker to reverse engineer the chip to obtain the decryption key.
In addition to being vulnerable to reverse engineering, storing a key on the chip may add production cost and complexity to chip manufacturers. For example, a battery must be used to store the encryption key in a SRAM FPGA. For an antifuse FPGA, extra fuses have to be blown to store the encryption key.
There is therefore a need to develop an IP protection scheme that achieves improved protection without using any decryption key.